• Specifications

2/120, 2/170 CPU Multibus

 10MHz 68010, no floating point chip, MMU, no on-board memory.  Multibus
  interface.

 The CPU board is entirely concealed within the chassis.  On one long edge, it
  has Multibus card-edge connectors.  On the other long edge, from top to
  bottom, it has: a header connector for the Sun-1 parallel keyboard and mouse,
  eight LEDs, and a 50-pin header connector (J1) for two serial ports.

 Jumper information:

 J100
  Sixteen pins, hardwired. All unjumped by default.

 J102
  1-2   Connects -5V to P1 -5V (default)
  3-4   Connects -5V to regulator

 J200    Crystal shunt                           JUMPED by default
  Removed for A.T.E. testing, installed for normal operation.

 J400
  1-2   selects 27128 EPROMs (default)
  3-4   selects 27256 EPROMs

 J700
  1-2   CPU drives P1 reset                     (jumped by default)
  3-4   P1 INT drives CPU reset                 (unjumped by default)
  5-6   serial arbiter enable                   (unjumped by default)
  7-8   arbiter bus config select               (unjumped by default)

  If the CPU board is used in conjunction with a Multibus DMA board (such as a
   disk or tape controller) that does NOT support the Common Bus Request
   (CBRQ), the CPU board must be configured such that it gives up the Multibus
   after every Multibus cycle, by jumping this jumper.  This also causes three
   additional wait states for each Multibus access.  When this jumper is
   unjumped, the CPU board retains bus mastership until a lower priority master
   requests it by asserting CBRQ.  Following a CBRQ, the CPU board yields
   mastership for at least one cycle.  Certain machine configurations
   (especially those with color) will be much slower if this jumper is jumped.

 J701
  1-2   CPU drives P1 BCLK                      (jumped by default)
  3-4   CPU drives P1 CCLK                      (jumped by default)

 J801
  Not used, unjumped by default.

 The two serial ports on J1 are usually labelled SIO-A and SIO-B on the back of
  the machine and appear as /dev/ttya and /dev/ttyb under SunOS.  The
  documented maximum output speed is 19200 bps.  All ports are wired DTE and
  are compatible with both RS-232C and RS-423, using Zilog Z8530A dual UART
  chips.  The pinout of J1 is:

  3    TxD-A       14  DTR-A       33  DD-B
  4    DB-A        15  DCD-A       34  CTS-B
  5    RxD-A       22  DA-A        36  DSR-B
  7    RTS-A       24  BSY-A       38  GND-B
  8    DD-A        28  TxD-B       39  DTR-B
  9    CTS-A       29  DB-B        40  DCD-B
  11   DSR-A       30  RxD-B       47  DA-B
  13   GND-A       32  RTS-B       49  BSY-B

 Power requirements are +5V @ 6A, and -5V @ 0.1A or -12V @ 0.1A.
 The last two are mutually exclusive.

  

   Last modified: 2000.10.25.19.54.54 CDT
     Server time: 2008.08.21.20.35.07 GMT