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SPARCcenter 2000


Date  
CPUs 1 - 20
Processor Mbus SPARCmodule   (microSPARC, hyperSPARC)
Clock speed 33, 36, 40, 50, 60, 75, 80, 90, 125, 150, 180 MHz
On-chip cache size   
External cache Up to 2 MB / Mbus module.
Memory 5 GB
Speed 2190 MIPS,   269 MFLOPS
@ 40 MHz + 1 MB (x8):   8047 SPECintRate92,   10600 SPECfpRate92
@ 50 MHz + 2 MB (x16):   21196 SPECintRate92,   28064 SPECfpRate92
Chassis type refrigerator
Bus 2 XDbuses,   20 slots.
4 Sbus slots @ 20 MHz / motherboard.
2 Mbus slots / motherboard.
Ports  
Internal storage  
Graphics  
Power supply  
Architecture sun4d
OS's supported First supported in Solaris 2.2 (SunOS 5.2).
Notes Code-name "Dragon".
Dual XDbus backplane.
Memory is not tied to the CPU modules but to the XDbus.
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   Last modified: 2002.10.26.11.58.39 CDT
     Server time: 2014.04.25.07.33.33 GMT